Alternate Functions

The I/O pins on any STM32 have great flexibility, and are configured via the “alternate functions” registers. As every model of STM32F chip has different numbers of pins and internal peripherals, the “alternate functions” matrix is only found in the data sheet, not in the programming references.

To access the alternate functions for each GPIO, alternate function mode must first be enabled via the MODER registers.

GPIOX_MODER (STM32F051)

Pin Function Code
Input mode (reset state) 00
General purpose output mode 01
Alternate function mode 10
Analog mode 11

After the alternate function mode is enabled above, the alternate functions are then selected per GPIO in the GPIOx_AFRL and GPIOx_AFRH registers.

GPIOA Alternate Function Matrix (STM32F051)

Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PA0   USART2_CTS TIM2_CH1_ETR TSC_G1_IO1       COMP1_OUT
PA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2        
PA2 TIM15_CH1 USART2_TX TIM2_CH3 TSC_G1_IO3       COMP2_OUT
PA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_IO4        
PA4 SPI1_NSS, I2S1_WS USART2_CK   TSC_G2_IO1 TIM14_CH1      
PA5 SPI1_SCK, I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2        
PA6 SPI1_MISO, I2S1_MCK TIM3_CH1 TIM1_BKIN TSC_G2_IO3   TIM16_CH1 EVENTOUT COMP1_OUT
PA7 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4 TIM14_CH1 TIM17_CH1 EVENTOUT COMP2_OUT
PA8 MCO USART1_CK TIM1_CH1 EVENTOUT        
PA9 TIM15_BKIN USART1_TX TIM1_CH2 TSC_G4_IO1        
PA10 TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2        
PA11 EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3       COMP1_OUT
PA12 EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4       COMP2_OUT
PA13 SWDIO IR_OUT            
PA14 SWCLK USART2_TX            
PA15 SPI1_NSS, I2S1_WS USART2_RX TIM2_CH1_ETR EVENTOUT        

GPIOB Alternate Function Matrix (STM32F051)

Pin name AF0 AF1 AF2 AF3
PB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2
PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3
PB2       TSC_G3_IO4
PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1
PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2
PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA
PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3
PB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4
PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC
PB9 EVENTOUT I2C2_SDA TIM2_CH4 TSC_G6_IO1
PB10 SPI2_NSS EVENTOUT TIM1_BKIN TSC_G6_IO2
PB11 SPI2_SCK   TIM1_CH1N TSC_G6_IO3
PB12 SPI2_NSS EVENTOUT TIM1_BKIN TSC_G6_IO2
PB13 SPI2_SCK   TIM1_CH1N TSC_G6_IO3
PB14 SPI2_MISO TIM15_CH1 TIM1_CH2N TSC_G6_IO4
PB15 SPI2_MOSI TIM15_CH2 TIM1_CH3N TIM15_CH1N

GPIO Alternate Function Selection Codes (STM32F051)

Code Alternate Function
0000 AF0
0001 AF1
0010 AF2
0011 AF3
0100 AF4 (Port A only)
0101 AF5 (Port A only)
0110 AF6 (Port A only)
0111 AF7 (Port A only)
1000 Reserved
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved

AFR Example

In this example entering “gpioa.” (provided by Svd2forth-v2) produces a listing of all the GPIOA registers, including the MODER and AFR registers, which are reproduced below.

  • GPIOA_MODER shows that GPIOA bits 9,10,11 and 12 are configured for alternate function mode (10), while the rest are input mode (00). For convenience, svd2forth-v2 groups the MODER register bit listing in groups of 2 bits.
  • GPIOA_AFRL shows that GPIOA bits 0 to 7 are in default AF0 (0000). For convenience, svd2forth-v2 groups the AFRL and AFRH register bit listings in groups of 4 bits.
  • GPIOA_AFRH shows that GPIOA bits 9,10,11 and 12 are in AF1 (0001).
gpioa.

GPIOA_MODER $02A80000
15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00
00 00 00 10 10 10 10 00 00 00 00 00 00 00 00 00

GPIOA_AFRL $00000000
07   06   05   04   03   02   01   00
0000 0000 0000 0000 0000 0000 0000 0000

GPIOA_AFRH $00011110
15   14   13   12   11   10   09   08
0000 0000 0000 0001 0001 0001 0001 0000

The reason for this config: This chip is running Mexrisp-Stellaris, which uses USART1 for the serial terminal connection including hardware flow control.

GPIO Pin Function
9 USART1_TX
10 USART1_RX
11 USART1_CTS
12 USART1_RTS