Let’s assume you’re new to STMicro’s STM32xx ARM MCU’s, you have a nice new STM32F0 Discovery board (about $15) and you have installed Mecrisp-Stellaris Forth by Mathias Koch http://mecrisp.sourceforge.net/ on it.
Now you’d like to begin programming, but where do you start, the STM32 documentation is vast, and there are a LOT of registers involved. As a matter of interest, a STM32F051 MCU as used in a STM32F0 Discovery Board lists around 470 unique registers, can you imagine the work involved in manually creating the Forth Words to manipulate them all ?
ARM created CMSIS-SVD to automate the job of telling “C” programs about STM32 MCU registers and register bit fields with SVDConv.exe.
- Are XML text files detailing all registers (or most of them at least) for MCU families and not individual parts.
- May be downloaded from https://github.com/posborne/cmsis-svd/tree/master/data/STMicro
- Programming language MCU specific files are created by applying XSLT stylesheets to the CMIS-SVD files.
Svd2forth-v2 by Terry Porter <firstname.lastname@example.org> 2016 for Mecrisp-Stellaris by Mathias Koch
- Was created to use CMSIS-SVD files for automated Mecrisp-Stellaris Forth memory-mapped Word production, making target software development far easier and less error prone, especially for Forth beginners.
- Enforces CMSIS compliant naming across all Mecrisp-Stellaris programs, enabling code reuse.
- Developed on FreeBSD but also tested on a Ubuntu 16.04.1 x64 VM. This is for Unix and won’t run on Microsoft Windows unless you install all the stuff that turns Windows into Unix.
Untar svd2forth-v2.tar.gz to a directory
run ‘make’ in this directory which will create the following four additional files. Note the size of “m” and “registers.text”
STM32F0xx.svd that has been ‘unfolded’. ARM supply them in a ‘condensed’ form which means that identical registers have missing details.
The memory mapped Forth file you upload to your target. Initially contains ALL the registers in your MCU and may be too large to upload to your target, depending on Flash size. After template.xml is edited (see below) and make run again, the size of “m” may be drastically reduced.
A register and bitfield programmer development reference file for registers selected in template.xml. Initially contains a list of ALL the registers in your ARM svd MCU file. After template.xml is edited (see below) and make run again, this file will only list the selected registers.
Initially contains a list of ALL the registers in your ARM svd MCU file. You edit this file by either commenting out, or deleting lines of registers you DON’T want to use in your project.
edit template.xml with ‘make edit’. Either comment out registers you don’t want by enclosing the line with “<- - register you don’t want - ->” or delete the entire line.
run ‘make’ again, this will rebuild “m” and “registers.text” to reflect the uncommented registers in “template.xml”
upload “m” to a STM32F0 Discovery board or chip depending on what you’re using. Typing ‘words’ in the serial terminal to your chip will show you the Words available.
Use “registers.text” as a programming aid by opening it read only and copy/paste register configs to your forth program.
Here all but the “COMP” register (as it’s so simple) have been commented out in template.xml and “make” was run. The file “m” is then uploaded to the Mecrisp-Stellaris system MCU via your serial terminal
The following (non bold text) are terminal screendumps:-
The word “comp.” lists the contents of the COMP_CSR register in the default one bit format (1b.)
It can be displayed with different print formats:-
Finally let’s read the registers.text file which shows how to set any of the bitfields in a copy/paste friendly way
|bit||pos arg||register name||bitfield name||bit||width|
|: %1||0 lshift||COMP_CSR bis! ;||\ COMP_COMP1EN||Bit 0||Width 1|
|: %1||1 lshift||COMP_CSR bis! ;||\ COMP_COMP1_INP_DAC||Bit 1||Width 1|
|: %xx||2 lshift||COMP_CSR bis! ;||\ COMP_COMP1MODE||Bit 2||Width 2|
|: %xxx||4 lshift||COMP_CSR bis! ;||\ COMP_COMP1INSEL||Bit 4||Width 3|
|: %xxx||8 lshift||COMP_CSR bis! ;||\ COMP_COMP1OUTSEL||Bit 8||Width 3|
|: %1||11 lshift||COMP_CSR bis! ;||\ COMP_COMP1POL||Bit 11||Width 1|
|: %xx||12 lshift||COMP_CSR bis! ;||\ COMP_COMP1HYST||Bit 12||Width 2|
|: %1||14 lshift||COMP_CSR bis! ;||\ COMP_COMP1OUT||Bit 14||Width 1|
|: %1||15 lshift||COMP_CSR bis! ;||\ COMP_COMP1LOCK||Bit 15||Width 1|
|: %1||16 lshift||COMP_CSR bis! ;||\ COMP_COMP2EN||Bit 16||Width 1|
|: %xx||18 lshift||COMP_CSR bis! ;||\ COMP_COMP2MODE||Bit 18||Width 2|
|: %xxx||20 lshift||COMP_CSR bis! ;||\ COMP_COMP2INSEL||Bit 20||Width 3|
|: %1||23 lshift||COMP_CSR bis! ;||\ COMP_WNDWEN||Bit 23||Width 1|
|: %xxx||24 lshift||COMP_CSR bis! ;||\ COMP_COMP2OUTSEL||Bit 24||Width 3|
|: %1||27 lshift||COMP_CSR bis! ;||\ COMP_COMP2POL||Bit 27||Width 1|
|: %xx||28 lshift||COMP_CSR bis! ;||\ COMP_COMP2HYST||Bit 28||Width 2|
|: %1||30 lshift||COMP_CSR bis! ;||\ COMP_COMP2OUT||Bit 30||Width 1|
|: %1||31 lshift||COMP_CSR bis! ;||\ COMP_COMP2LOCK||Bit 31||Width 1|